Electronics - Peak detector circuits and models

19-03-2016, Changed; 14-04-2018 to 19-04-2018

Modelling tools used;

  • TI-Tina 9, SiMetrix 6.20 and LT Spice IV - These tools are the free versions or are free. They produce similar results but of cause they do not model circuit board parasitics unless components are added to represent the PCB parasitics. Therefore take care with the results and ensure you figure out what you want and what you expect before you start any modelling. 
  • By comparison, obviously, there are some points you can not test directly on a real circuit because the test probe will effect the circuit. So do consider what you can test and what is happening where you would have liked to have tested if there were such a thing as an ideal test probe.
See; http://www.andrew-lohmann.me.uk/engineer/electronics/electronics-simulation-judgement

TI-Tina 9 conventional peak detector;

 This circuit is approximately what I have used for some decades. It works well over a limited signal range. 
This circuit is different to what I have done before and hopefully an improvement on that. (AL-0018-01B).

The relocation of C1 (from between -in and output) and the addition of R5 components both reduces overshoot and improves accuracy it can be seen. The relocation of C1 and reduction of the capacitors value has reduced overshoot and the circuit's bandwidth is less compromised. The output can be taken from U2 or taken from VF2 that is cleaner using a high input impedance circuit. 

C2 is also additional and has no benefit but does reduce some ringing. The capacitor is placed to be like the transistors are placed in other circuits on other pages and is comparable to the inter-electrode capacitance of those transistors. It has not got quite the same cleaning up of waveforms effect that the smooth transition in gain has in the circuit that uses transistors with there consequent variable feedback.

MCP651 op-amp is a Microchip part that can be used because there is also a Texas Instruments part used in this circuit. But the same microchip op-amp model can fail with a time-step error when used with SiMetrix but always failed with a similar error with LT Spice tool, I found.



Above circuit with +-250uV pk-pk 100Hz square wave input. Gain x10.
  • The op-amp's loop gain will be high (about 500 = 120mV/250uV by inspection).
  • We would like the circuit to work to 1KHz. So the Gain Bandwidth product in this case required is about 500KHz
  • The Gain Bandwidth product of the op-amp is 50MHz giving a factor of 100. Due to this one aspect the accuracy is about 1% therefore consequently.
A rough idea of what this circuit can do but we have not considered loop gain of the op-amp but that is not specified. There will be some intangibles such as extra circuit components shown with this sort of complex function block. But we now have enough to say this design may be good for 1% accuracy at up to a few 100Hz over 100:1.


Above circuit with +-250uV pk-pk 100Hz square wave input. The gain is x10. Same waveform as above but zoomed in.

 It can be seen that the circuit is at lowest limit of it's signal range and the output is barely usable.

Above circuit +-25mV 100Hz. Gain x10 zoomed in.

It can be seen that the output does overshoot but does not ring much. There was a very small bit of ringing without C2 fitted at about 690mS but that was not detrimental so the capacitor is not beneficial and could introduce some compromise? 
The capacitor may be placed on a PCB but not fitted unless something arises in practice?
Above circuit +-25mV 100Hz. Gain x11 same waveform but zoomed out. 

The short spike is where the work of peak detection was done it is not possible to correct the overshoot without compromising something else more. The over shoot in any case is trivial <1%.
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SiMetrix 6.20 - the circuit above refined and modelled with a similar tool.

 

This is a conventional peak detector but after simulating using SiMetrix sice circuit modelling tool C1 and R1 have been moved and R4 added. The op-amp is a higher input impedance type than the Texas Instruments one used above. (AL-0017-01D).
 

The circuit appears to be consistent to <1mV with an offset within the tolerance of the operational - amplifier in this case 8mV. This is a model and C1 may be too small when real circuit board parasitic capacitances are included. This circuit is improved further for small signals if R1 is reduced to 470K - the first waveform shows the problem.


I reckon that a 470K feedback would be too high an impedance given that the negative input of the amplifier's voltage is following the positive input and would therefore be susceptible to circuit board parasitic capacitance. I have not included modelled waveforms which are in any case better for small signals than the those for the high feedback resistance circuit shown. In practice the waveforms may look like those for the circuit above this circuit with the higher feedback impedance, though.

An output buffer is not shown fitting but is is beyond the capacity of this free version of the modelling tool to include it. In any case circuits to be modelled should be kept to the critical part of the function that requires modlelling in order for the modelling to complete in good time.

The op-amp will be changed to a more accurate MCP651 although it has a reduce Gain Bandwidth Product a little.
  The diagram above is from the model. +-2.5mV 100Hz input. Is good for this type of
circuit. I have zoomed in and it can be seen that the offset is increased by -25mV.

The negative input of the op-amp will have significant impedance compared to the feed-back. The amplifier is configured as a follower so that negative input voltage changes against input capacitance so that is most likely effecting the small signal performance.

  The diagram above is from the the model. +-250mV 100Hz input.

 Is good for this type of circuit. It can be seen that the circuit at full amplitude has settled in 1mS with a large output this corresponds to >250Hz bandwidth.

  The diagram above is from the the model. +-400mV 100Hz input the circuit 
is now limited by the power supply voltage. But the model is still operating.
 
This circuit performs well. The model also works realistically although there is clipping by powers supply voltage. The ramping up would be expected because the drive voltage required cannot be achieved.

The first circuit also shows a ramping up and this may be entirely due to the capacitor C2 that would be expected. This ramping behaviour is not apparent in the second circuit.

There is always value in having a theory but a theory will difficult to write or say until it answer's enough questions and the engineer's mind is clearer about what is happening. But it is to express what you have found so far to others using imprecise words like, like, reckon and as-if. I have said to someone, I do understand but please help me express it in a better way?
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Tina TI - Putting two peak detectors together to make a positive and negative peak detector. The higher of the two voltages is the peak voltage.

See separate page; Pos Neg Peak detector circuits and models


TWO PEAK-DETECTORS (AL-0018-02K) the greater voltage of either the positive or negative voltages is the peak. The circuit shares one hold capacitor but there is no apparent interaction between the two peak detectors. As before I have not included capacitors across D2 and D4 because they were not beneficial and could have a marginal dis-benefit - but it is reasonable to place do-not-fit parts on a PCB so that they could be fitted subsequently? In this case these amplifiers recover from the output being saturated quickly so I have  also removed D1 and D3 and thereby have been able to improve and simplify the feedback loop.

+-250uV 100Hz

This circuit with choice of op-amp would work with a lower supply voltage than the Two peak detectors approach I have modelled on another page.
+-250uV 100Hz input x30 - Zoomed Y

The amplifier offset voltage is apparent in the settling time whilst the coupling capacitor deals with it. There are other offset errors apparent. 

+-250uV 100Hz Zoomed in to the op-amp outputs.
 Offset difference is apparent because the peaks are different heights.

The LMV842 input bias current is specified over the temperature range. This is important because the vibration sensor is very high impedance. This particular IC also has a Tina-TI spice model. 

+-25mV 100Hz square wave input. Gain is about x30 as above.

The capacitor C3 is settling to the op-amp offset voltage as above.

+-25mV 100Hz square wave input - Zoomed in Y. Gain is about x30 as above.

The coupling capacitor settling time is larger for a larger input signal so what is happening is unclear?  


+-25mV 100Hz square wave input - Zoomed in. Gain is about x30 as above.

These are the op-amp's charging pulses after the coupling capacitor has had time to settle.
  • Brown - peak detector 1 op-amp.
  • Green-ish - peak detector 2 op-amp. The consequence of a little offset error voltage means this side is not doing so much work.
  • Green - Peaks output.
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The first solution I had was not worth drawing but I have drawn it up below (AL-0018-01A). D3 & D8 form a voltage doubling rectifier. D1 & D2 provide temperature compensation. This circuit will be non-linear and tend to expand the peaks with the small signal voltage being used. In this example there is only one or two of these test units made and the circuit will give an indication of vibration and increasing vibration so it is worth considering.
 This has not been modelled at most it might be sketched on scrap paper to show
a discounted idea. I have modelled it in the past using pen, paper and calculator
 and may have used the circuit as part of a capacitive humidity sensor.

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What can be concluded

Almost certainly different combinations of things shown could improve these circuits further. The capacitive coupling directly to the peak detectors was not a good move for large signals - this probably something to do with the op-amp's with the diodes not drawing current in a symmetrical way when the signal is too large. But inversion or gain in the peak detector is a good move, whether I have figured out quite why that is so yet, and that does need to be figured out. But there is some point where refinement is enough and the designer must stop and move on to the next problem. That is the hardest thing to do.

The TED talk linked below is interesting. The speaker discusses how it is necessary to be open to trying many things (procrastinate he says) in order to be a successful original thinker. I think the speaker is coming at Temperament (that I discuss on my website) but by another way.



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  2. April 2018 - Additional diagram added at the bottom of the page plus tidy up.

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